Interlaken IP Subsystem
High speed chip-to-chip interface protocol with scalable bandwidth, low latency and reliable data transfer over serial links. The latest generation supports up to 1.2 Tbps bandwidth with support for NRZ and PAM4 serial links.
High speed chip-to-chip interface protocol with scalable bandwidth, low latency and reliable data transfer over serial links. The latest generation supports up to 1.2 Tbps bandwidth with support for NRZ and PAM4 serial links.
Interlaken IP is used by many applications including NPU, traffic management and switch fabrics. Alphawave Semi (through the OpenFive acquisition), was a founding member of the Interlaken Alliance and supports silicon-proven Interlaken IP with over 75+ tier 1 customers on various technology and process nodes. The ZetaCORETM IP includes a validation platform supporting up to 1.2 Tbps (64K channels and 48 SerDes lanes) using a wide range of transceiver speeds and Forward Error Correction (FEC) engines.
Extending on the 8th generation of its Interlaken IP core, Alphawave Semi has now introduced a low latency version of the Chip-to-Chip (C2C) and Die-to-Die (D2D) connectivity Interlaken IP used across many applications. Cutting edge technologies such as High Performance Computing (HPC) clusters, Artificial Intelligence (AI)/Machine Language (ML) chip clusters, Internet of Things (IoT) edge devices, networking, and switching fabrics are demanding high throughput data transfer from one chip to another at very Low Latency (LL). The Interlaken-LL includes a validation platform supporting up to 256 Gbps.