OpenFive Launches Die-to-Die Interface Solution for Chiplet Ecosystem

OpenFive Launches Die-to-Die Interface Solution for Chiplet Ecosystem

  • Features IOs running at up to 16Gbps (effective throughput of ~1.75Tbps/mm)
  • Features extremely low latency and <0.5pJ/bit offering best power performance benchmarks


SAN MATEO, Calif., April 5, 2021 – OpenFive, the leading provider of customizable, silicon-focused solutions with differentiated IP, today announced the launch of a Die-to-Die (D2D) PHY that complements the company’s existing D2D Controller to offer complete D2D interface solutions for various packages including substrates and interposers.

The new D2D PHY helps disaggregate large SoC die into smaller die, resulting in better yield, cost and power savings. It features up to 16Gbps NRZ signals with clock forwarding architecture. Each channel, comprising of 40 IOs, can provide effective throughput of up to ~1.75Tbps/mm.Users can stack up multiple channels to further increase overall throughput. The PHY also features built-in PLL, programmable output drivers, and link training state machines.

“The D2D subsystem, including both the controller and PHY, provides best-in-class latency, performance and power profile for various IO, CPU and analog chiplets,” said Ketan Mehta, Sr. Director, Product/Application Marketing, SoC IP, at OpenFive.

“OpenFive’s die-to-die connectivity IP solution will enable widespread integration of proven solutions from chiplet ecosystem partners,” said Mohit Gupta, SVP and GM, SoC IP at OpenFive. “As a custom ASIC and IP provider, OpenFive is well-positioned to provide an entire chiplet solution to our customers at any stage of development, whether it be during design, integration, manufacturing, or testing of Known-Good-Die (KGD).”

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About OpenFive
OpenFive, a SiFive Business Unit, is uniquely positioned to deliver highly competitive SoCs with its spec-to-silicon design capabilities, customizable IP for AI/Cloud/HPC/storage/networking applications, and processor agnostic domain-specific architectures. The OpenFive IP portfolio includes High-Bandwidth Memory (HBM2/E), Die-to-Die (D2D) interface IP for multi-die connectivity including chiplets, low-latency, high-throughput Interlaken interface IP for chip-to-chip connectivity, 400/800G Ethernet MAC/PCS subsystems and USB controller IP.OpenFive offers end-to-end expertise in architecture, design implementation, software, silicon validation and manufacturing to deliver high-quality silicon in advanced nodes down to 5nm. For more information, please visit


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INK Communications for SiFive