HBM2/2E IP
- High bandwidth, low latency communications with high-density off-chip memory for graphics, high performance computing and high-end networking
HBM2/2E PHY Specifications
- Integrated HBM controller and HBM PHY subsystem solution supporting HBM2 and HBM2E JEDEC spec for
a wide range of technology and foundry nodes.
- SiFive plays a key role in enabling industry applications that leverage HBM 3D-stacked DRAM technology:
- Early advocate of 2.5D and 3D ASIC design technologies: developer of the industry’s first successful 2.5D SOC SiP
HBM2/2E Interface
- CMOS I/O with programmable drive strengths
- 3.2Gbps/1.6GHz DDR with light output loading
- Up to 5mm interposer trace length support meeting 3.2Gbps per pin date rate
- Electrically compatible with JEDEC HBM2/2E spec
- Optional differential receiver
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