Join us in this webinar to learn more about our USB 3.2 IP solution, including Retimer, for high-speed consumer applications. We will review the IP engineering features, operations, configurations, protocols and implementation guidelines in detail. Alphawave Semi’s USB 3.2 Gen2 Retimer IP cores are compliant with the USB 3.2 Appendix E standard. USB 3.2 Gen 2 supports up to 10 Gbps of bandwidth. It includes a USB 3.2 Gen2 single lane PCS layer and supports all low power states.
- Features of the USB 3.2 Gen2 IP cores
- Implementation guidelines – integration and testing
- Market outlook, applications and other details
Consumer product chip designers, high-speed interface IP designers, IP application engineers, IP architects and system engineers.
Vikas Aravind Kulkarni, Director, SoC IP Engineering, SiFive, Inc.
Sanket Apurvabhai Shah, Verification Lead, SiFive, Inc.
Ketan Mehta, Director, SoC IP Product Marketing, SiFive, Inc.
Eric Esteve, Founder of IPnest and Analyst at SemiWiki