ZetaCORE Interlaken ASIC IP Core Factsheet

Interlaken IP (Chip-to-Chip Interface)

The eighth generation of ZetaCORE Interlaken IP core improves the bandwidth to over 1.2Tb/s while at the same time reducing the area and power. Building upon the flexible and robust architecture, the The ZetaCORE Interlaken IP core has “pipe efficiency” and “67-bit SerDes slice”, which saves significant area while at the same time allows the IP to run at a lower frequency thus saving power. The “pipe efficiency” feature saves significant area by reducing the number of pipes (64b internal datapaths) by efficiently mapping the pipes to SerDes lanes while reducing the required clock frequency. The “67b SerDes slice” feature allows the IP to operate the SerDes slice functionality in a single clock cycle (2 cycles previously) thus reducing required clock frequency