“An Overview of Analog & Mixed-Signal Design in deep sub-7nm Technology”
The paradigm shift of semiconductor industry from Analog based design to digital designs with higher transistor density was predicted around the early 21st century. With such growth, it was also predicted that the Analog would be ceased out and digital will be the design choice for an SoC.
Currently, as transistor technologies are shrinking below 7nm, the requirement for faster interfaces with high-speeds (such 112 Gbps or more) has become very much essential. Designing such highspeed interfaces are very much challenging in digital domain, as the supply voltage is scaled down with tightened power constraints in advanced technologies. These factors challenge the usage of pure digital design circuitry for e.g. I/O, PLL, DLL etc with the constraints mentioned above in an SoC design.
Emerging applications like Artificial Intelligence (AI), High-Performance Computing (HPC), HighSpeed Networking etc., multi-cross functional features are added in SoCs. For implementing such features, designers are leveraging optimization techniques in RTL logic, standard cell design, physical design, complex DRC rules and double patterning methods. But these optimizations techniques hit the wall when it comes to I/O design. Therefore, there is a big need for Advanced Analog/ Mixed Signal design techniques in the Industry.
Download the Full PDF to Read More