Die-to-Die (D2D) IP Subsystem

Die-to-Die IP Subsystem offers a unique value proposition in terms of low power, high throughput, and low latency links enabling faster time to integration for heterogenous chipset connections in wired communications, Artificial Intelligence (AI), and High Performance Computing (HPC) applications.

D2D IP Subsystem

Die-to-Die IP Subsystem is targeted for heterogenous chiplet solutions in wired communications, AI, and HPC applications. With recent advances in package technologies, it is possible to route high-speed signals within a package connecting multiple dies either on an interposer or on an organic substrate. Die-to-Die IP Subsystem offers a unique value proposition in terms of low power, high throughput and low latency links enabling faster time to integration.

D2D PHY IP

D2D PHY signals are single-ended (Single Duplex) and are based on HBM Memory Electrical IOs
Each channel is made up of 42 pairs of TX/RX signals that run at configurable speed up to 16 Gbps contributing up to ~1.75 Tbps/mm
Channel lengths support up to 5 mm with latency less than 5 ns (Other combinations are available)
Best in the industry less than 0.5 pJ/bit power consumption
Built-in PLL to support differential clock forwarding
Self-contained initialization and calibration state machines
No requirement of Forward Error Correction (FEC) IP as signal supports channel BER up to 1E-21
Programmable output drivers
Compatible to various parallel wire specifications in the industry

D2D PHY IP Block Diagram

Download D2D PHY IP Product Brief

D2D Controller IP

Ultra-high-bandwidth and performance (For example, 1024-bit AXI interface at 2 GHz can provide up to 2 Tbps)
Ultra-low latency including TX and RX depending on the optional FEC module to improve BER
Support for the SerDes rates up to 112 Gbps (CEI-112G-XSR) and aggregation support up to 48 lanes
Independent SerDes lane enable/disable and fully programmable SerDes lane mapping
Flexible AXI interface options including 64b, 128b, 256b, 512b and 1024b
Optional In-band and Out-of-Band flow control
Built-in error detection and interrupt structure
Optional retransmission module for error free transmission
Configurable error injection mechanisms for testability
Debug Features: PRBS generators/checkers and loopback support for both data and flow control

D2D Controller IP Block Diagram

Download D2D Controller IP Product Brief

SerDes Partners

IP Customization

If you already have a specific SOC IP spec in mind, our team can help you to customize the controller IP as per your requirements.

Alphawave Semi™ is a global leader in high-speed connectivity for the world’s technology infrastructure. Our IP and custom silicon solutions meet the needs of global tier-one customers in data centers, compute, networking, AI, 5G, autonomous vehicles, and storage.
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