AresCORE UCIe Die-to-Die PHY IP

AresCORE is a market leading extremely low-power, low-latency Universal Chiplet Interconnect Express (UCIe™) Die-to-Die PHY IP designed by Alphawave Semi for very high bandwidth connections between two dies that are on the same package. Its main target applications include, but are not limited to:

  • High-Performance Computing (HPC)
  • Data Centers
  • Artificial Intelligence (AI)
  • Networking

AresCORE UCIe Die-to-Die (D2D) PHY IP

AresCORE UCIe D2D PHY IP is the physical layer to enable Alphawave Semi’s Complete UCIe Solution for an open and robust chiplet ecosystem.

The AresCORE PHY IP is optimized for high-bandwidth density – Up to 36Gbps data-rate-per-lane, low-power, low-latency multi-module PHY and leverages silicon-proven analog IPs.

The AresCORE PHY IP can be configured to support advanced packaging such as Silicon Interposer, RDL Interposer, Integrated Fan-Out and Silicon Bridge for maximum density, and organic substrates for the most cost-effective solution covering all market segments.

The AresCORE PHY IP is available in leading-edge foundries across multiple technology nodes.

AresCORE Block Diagram

High Bandwidth Density and Data Rates

The AresCORE UCIe D2D PHY IP provides

  • – High Tb/s of bandwidth per mm of shoreline, >11.8Tbps/mm (Advanced Package) and >2Tbps/mm (Standard Package)
  • – High data-rate-per-lane, up to 36Gbps

Package Configurability

The AresCORE UCIe D2D PHY IP supports

  • – UCIe Standard Package (2D) with 16-bit and 32-bit modules
  • – UCIe Advanced Package (2.5D) with 32-bit and 64-bit modules

Energy Efficiency

The AresCORE UCIe D2D PHY IP is an extremely power efficient, low-latency interconnect allowing the connection between two dies through short-reach low-loss channels. Our architecture allows SoC teams to reduce IO complexity and save power.

Fully Integrated Solution

  • – Equipped with full calibrations, training, DFT, and reliability features
  • – Optimized for E/W and N/S implementations
  • – Delivered as a subsystem to support RDI or pre-integrated with streaming or PCIe/CXL controller

Robust Chiplet Ecosystem

  • – Alphawave provides a platform for electrical, physical form factor, and protocol compliance
  • – Complete set of test vehicles for interoperability testing

Comprehensive Testability

  • – The AresCORE UCIe D2D PHY IP is compliant with IEEE 1149 boundary scan testing
  • – The Built-In Self-Test (BIST), internal and external loopback, and non-destructive eye diagram provide on-chip testability and visibility into channel performance
  • – Features for KGD (Known Good Die) testing

Typical Applications

The AresCORE UCIe D2D interconnect enables SoC developers to break the boundaries of the reticle limit by including multiple dies in the same package. This multi-die approach to silicon design allows for better yielding, smaller purposeful dies vs. traditional SoCs. The main target applications AresCORE UCIe D2D interconnect include, but are not limited to:

  • – AI accelerators
  • – Server class CPUs
  • – Network switches designed for large compute
  • – FPGAs
  • – 5G base stations
  • – IO and optical transceivers

Download AresCORE UCIe D2D PHY IP Factsheet