AresCORE is a market leading extremely low-power, low-latency Universal Chiplet Interconnect Express (UCIe™) Die-to-Die PHY IP designed by Alphawave Semi for very high bandwidth connections between two dies that are on the same package. Its main target applications include, but are not limited to:
AresCORE UCIe D2D PHY IP is the physical layer to enable Alphawave Semi’s Complete UCIe Solution for an open and robust chiplet ecosystem.
The AresCORE PHY IP is optimized for high-bandwidth density – Up to 64 Gbps data-rate-per-lane, low-power, low-latency multi-module PHY and leverages silicon-proven analog IPs.
The AresCORE PHY IP can be configured to support advanced packaging such as Silicon Interposer, RDL Interposer, Integrated Fan-Out and Silicon Bridge for maximum density, and organic substrates for the most cost-effective solution covering all market segments.
The AresCORE PHY IP is available in leading-edge foundries across multiple technology nodes.
The AresCORE UCIe D2D PHY IP provides
The AresCORE UCIe D2D PHY IP supports
The AresCORE UCIe D2D PHY IP is an extremely power efficient, low-latency interconnect allowing the connection between two dies through short-reach low-loss channels. Our architecture allows SoC teams to reduce IO complexity and save power.
The AresCORE UCIe D2D interconnect enables SoC developers to break the boundaries of the reticle limit by including multiple dies in the same package. This multi-die approach to silicon design allows for better yielding, smaller purposeful dies vs. traditional SoCs. The main target applications AresCORE UCIe D2D interconnect include, but are not limited to: