SigmaCORE HBM3 Controllers

The SigmaCORE High-Bandwidth Memory Generation 3 (HBM3) controller is ideal for applications involving graphics, high-performance computing, high-end networking, and communications that require very high memory bandwidth, lower latency, and more density. The controller can be delivered as part of a complete HBM3 memory subsystem with an integrated HBM3 PHY.

The SigmaCORE Integrated HBM controller supports HBM3, HBM2E, and HBM2 JEDEC specifications for a wide range of technology and foundry nodes. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first multiple successful 2.5D SOC System in Package (SiP) demonstrations, Alphawave Semi plays a key role in enabling industry applications that leverage HBM 3D-stacked DRAM technology.

Protocol controller

  • JEDEC (JESD235C and JESD238) HBM3/2E/2 DRAM specification compliant
  • Pseudo-channel mode support
  • Multi stack HBM3/2E/2 memory support
  • Power down self-refresh modes
  • Low latency controller features
  • Per channel data rate of up to 7.2 Gbps per pin for HBM3 and 3.2 Gbps per pin for HBM2E
  • Configurable independent channels
  • Memory access optimizations for bandwidth efficiency
  • Configurable error injection mechanisms for testability
  • DFI-like controller/PHY interface
  • Supports 1:1, 1:2, and 1:4 Controller/PHY frequency ratios
  • Memory die diagnostic features
  • JTAG connectivity for IEEE-1500 access, lane repair, training and loopback test modes
  • Multiple in-built test and diagnostic features