SigmaCORE HBM3 PHY

The SigmaCORE High-Bandwidth Memory Generation 3 (HBM3) controller is ideal for applications involving graphics, high-performance computing, high-end networking, and communications that require very high memory bandwidth, lower latency, and more density. The controller can be delivered as part of a complete HBM3 memory subsystem with an integrated HBM3 controller.

SigmaCORE

The SigmaCORE Integrated HBM controller supports HBM3, HBM2E, and HBM2 JEDEC specifications for a wide range of technology and foundry nodes. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first multiple successful 2.5D SOC System in Package (SiP) demonstrations, Alphawave Semi plays a key role in enabling industry applications that leverage HBM 3D-stacked DRAM technology.

PHY Layer

  • Ultra-low latency
  • Easily portable across technologies
  • Includes Input/Output (IO), Phase-Locked Loop (PLL), and Delay-Locked Loop (DLL)
  • Coarse and fine grain IO training
  • Low-power HBM memory and PHY modes
  • Complies to ESD requirements
  • Loopback support for testability
  • JEDEC (JESD235C and JESD238) HBM3/2E/2 DRAM specification compliant
  • Optional support for LLHBM
  • Process nodes supported – TSMC 16/12nm, 7/6nm, 5/4nm, GF 14/12nm, GF 22FDx

Die-to-Die Interposer IO

  • CMOS IO with programmable drive strengths
  • Up to 7.2 Gbps/pin (HBM3) and 3.2 Gbps/pin (HBM2E)
  • Up to 5mm interposer trace length support meeting > 3.2 Gbps per pin date rate
  • Electrically compatible with JEDEC HBM3/2E/2 specification
  • Optional differential receiver