HBM3/2E/2 IP Subsystem

The HBM3/2E/2 IP is ideal for applications involving graphics, high-performance computing, high-end networking, and communications that require very high bandwidth, lower latency, and more memory density.

HBM3/2E/2 IP SPECIFICATIONS

Integrated HBM controller and HBM PHY subsystem solution that supports HBM3, HBM2E, and HBM2 JEDEC specifications for a wide range of technology and foundry nodes. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first multiple successful 2.5D SOC System in Package (SiP) demonstrations, Alphawave Semi plays a key role in enabling industry applications that leverage HBM 3D-stacked DRAM technology.

HBM3/2E/2 ASIC SiP

Protocol Controller

  • JEDEC (JESD235B) HBM3/2E/2 DRAM specification compliant
  • Pseudo-channel mode support
  • Multi stack HBM3/2E/2 memory support
  • Power down self-refresh modes
  • Low latency controller features
  • Per channel data rate of up to 3.2 Gbps/pin
  • Configurable independent channels
  • Memory access optimizations for bandwidth efficiency
  • Configurable error injection mechanisms for testability
  • DFI-like controller/PHY interface
  • Supports 1:1 and 2:1 PHY/Controller frequency ratios
  • Memory die diagnostic features
  • JTAG connectivity for IEEE-1500 access, lane repair, training and loopback test modes
  • Multiple in-built test and diagnostic features

PHY Layer

  • Ultra-low latency
  • Easily portable across technologies
  • Includes Input/Output (IO), Phase-Locked Loop (PLL), and Delay-Locked Loop (DLL)
  • Coarse and fine grain IO training
  • Low-power HBM memory and PHY modes
  • Complies to ESD requirements
  • Loopback support for testability
  • JEDEC (JESD235B) HBM3/2E/2 DRAM specification compliant
  • Optional support for Low-Latency High-Bandwidth Memory (LLHBM)
  • Process node supports TSMC 16/12nm, TSMC 7nm, GF14/12nm, GF22FDx

Die-to-Die (D2D) Interposer IO

  • CMOS IO with programmable drive strengths
  • 3.2 Gbps/1.6 GHz Double Data Rate (DDR) with light output loading
  • Up to 5mm interposer trace length support meeting > 3.2 Gbps per pin date rate
  • Electrically compatible with JEDEC HBM3/2E/2 specification
  • Low latency controller features
  • Optional differential receiver

IP Customization

If you already have a specific SOC IP spec in mind, our team can help you to customize the controller IP as per your requirements.