HBM3/2E/2 IP Subsystem

The HBM3/2E/2 IP is ideal for applications involving graphics, high-performance computing, high-end networking, and communications that require very high bandwidth, lower latency, and more memory density.


Breaking through the memory wall, the Alphawave Semi HBM3 memory subsystem supports data rates up to 8.4 Gbps per data pin. The HBM3 interface features 16 independent channels, each containing 64 bits for a total data width of 1024 bit.

Integrated HBM controller and HBM PHY subsystem solution that supports HBM3, HBM2E, and HBM2 JEDEC specifications for a wide range of technology and foundry nodes. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first multiple successful 2.5D SOC System in Package (SiP) demonstrations, Alphawave Semi plays a key role in enabling industry applications that leverage HBM 3D-stacked DRAM technology.

IP Customization

If you already have a specific SOC IP spec in mind, our team can help you to customize the controller IP as per your requirements.