10G/40G/100G/400G OTN Digital Wrappers
10G/40G/100G/400G OTN Digital Wrappers support the latest standard OTUCn framer with backward compatibility to NxOTU4 signals.
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400G OTN Digital Wrappers
Alphawave Semi offers a dynamically reconfigurable OTUC4, 2xOTUC2, and 4xOTU4 OTN digital wrapper IP core solution. The IP core is a perfect choice for carrying 400/200GE (IEEE 802.3bs) signal, 100GE signal over Optical Transport Network. Software can configure the IP core into 1xOTUC4 mode, 2xOTUC2 mode and 4xOTU4 mode dynamically.
Core Support
The Core supports 3 levels of OH insertions and extractions : register programming, memory programming and external programming via a dedicated OH port. It comes with Optional GFEC/HDFEC core, which can be bypassed when connected with external high-gain FEC or Coherence module. It also comes with optional FlexO-1/2/4-SR Line interface or OTLC4 interface. The OTN core supports full alarm and OH inserts and extracts as specified in ITU G.709 and ITU G.798.
The diagram shows an application example of mapping 400GE/2x200GE/4x100GE onto OTUC4 Core.
100G OTN Digital Wrappers
The OTU4 Digital Wrapper IP Core offers 100G/s client transport rate over Optical Transport Network (OTN), specified by ITU-T G.709 recommendation.
40G OTN Digital Wrappers
The 40G OTN Digital Wrapper IP Core offers 40G/s client transport rate over Optical Transport Network (OTN), specified by ITU-T G.709 recommendation.
10G OTN Digital Wrappers
The 10G OTN Digital Wrapper IP Core offers 10G/s client transport rate over Optical Transport Network (OTN), specified by ITU-T G.709 recommendation.
Key Advantages
- Cost effective – Low cost replacement for multiple ASICs solution
- Power efficiency – Low power replacement for multiple ASICs solution
- Higher port density per card – space efficiency
- Timing transparency on each lane.
Core Features
- Compliant with G. 709 and G.798
- Small footprint suitable for ASIC or FPGA realization
- Supported bus width options: 10G-4 or 8 bytes, 40G-16 or 32 bytes, 100G-40 or 64 bytes, 400G-128 bytes
- Optional processor interface with 32-bit registers
- Optional FEC generation/processing