Composable SoC

Alphawave Semi has a broad selection of leading-edge IP controller blocks and interfaces to which you can add your own custom accelerator, interface, or security IP.  For CPU subsystems, we have collaborated with Arm as part of the Arm Total Design ecosystem based on Arm Neoverse Compute Subsystems (CSS) for faster development time with lower risk.

Key Subsystems of Composable SoC

The composable SoC consists of many key subsystems:  CPU subsystem, accelerators, memory Interfaces, host interfaces, network interfaces, platform controller, peripherals, and (in the case of chiplets) die-to-die (D2D) interfaces.  Each of these can be specifically chosen – or integrated with customer’s IP – and tuned to optimize power and performance for specific workloads.  As important as the subsystems themselves is the on-chip interconnect that connects them all together.  In the end, balanced performance without bottlenecks between the subsystems and outside world is key to the SoC solution.


  • CPU Subsystem
  • Accelerators
  • Memory Interface
  • Host Interface
  • Network Interface
  • On-Chip Interconnect
  • Platform Controller
  • Peripherals
  • D2D Interface


  • CPU Subsystem optimized for power, performance, area (PPA)
    • Arm Neoverse Compute Subsystems (CSS)
    • Arm A/R/M-profile processors
  • Custom Accelerators
    • Customer defined
  • Memory Interfaces
    • HBM3, DDR5, LPDDR5
    • Up to PCIe Gen6 / CXL 3.0
  • Host Interface
    • PCIe Gen6/5/4 PHY & Controllers
    • 112G & 224G Multi-protocol SerDes
    • Co-packaged Optics (CPO)
  • Network Interface
    • 112G & 224G Multi-protocol SerDes
    • 1.6T/800G/400G to 10M Ethernet/CPRI/FlexIO
    • Co-packaged Optics (CPO)
  • On-Chip Interconnect
    • Arm AMBA CHI, AXI, CMN-700, NIC-700
    • Ateris FlexNoC
  • Platform Controller
    • Arm Confidential Compute Architecture (CCA)
    • Arm Manageability Control Processor (MCP)
    • Arm System Control Processor (SCP)
    • proteanTecs System Insights and Analytics
    • Boot Flow
    • JTAG Debug
    • One-Time Programmable (OTP) Memory
  • Peripherals
    • AXI CHI, ACE, AXI, AHB, APB buses
    • DMA
  • D2D Interface
    • UCIe Standard and Advanced
    • Low power, low latency, streaming


  • Advanced 2.5D Packaging
    • TSMC Chip-on-Wafer-on-Substrate (CoWoS®)
    • TSMC Integrated Fanout (InFO)
    • Samsung iCube™
    • ASE Fan-Out Chip on Substrate (FOCoS)
  • 3D Stacking
  • Stacked Die
  • Package-on-Package (PoP)
  • Fan-Out Wafer-Level Packaging (FOWLP)
  • Wafer-Level Chip Scale Package (WLCSP)
  • Multi-Chip Modules (MCM)
  • Signal Integrity (SI) analysis
  • Power Integrity (PI) analysis
  • Flip-Chip Packaging
  • Ceramic and Organic Substrates
  • Through-Silicon Vias (TSVs)
  • Wire Bonding and Microbump Technologies

Composable SoC
Solution Benefits

  • Workload Customization
  • Heterogeneous Compute Support
  • Flexibility for Industry-specific Requirements
  • Adaptation for Emerging Technologies
  • Resource Optimization / Reduced Hardware Redundancy
  • Optimized Interfaces
  • Improved System Utilization
  • Enhanced Energy Efficiency
  • Enhanced Security
  • Reduced Time-to-Market
  • Cost Efficiency in High Volumes
  • IP Reuse
  • Scalability
  • Advanced Quality Levels
  • Fault Tolerance and Resilience

Future Technologies

Alphawave Semi is taking a leadership role in defining and driving next generation interfaces and standards to advance the computing industry, particularly in the areas of AI/ML.  This means you’ll be on the leading edge when these technologies are mature enough to integrate into the composable SoC.

Examples include:

  • PCI-SIG Workgroup for Optical PCIe
  • New short-reach and low-latency connectivity standards at IEEE
  • New standard body to enhance Ethernet specifically for AI & HPC at scale: UltraEthernet Consortium
  • Universal Chiplet Interconnect Express (UCIe) for chiplet interconnect
  • Packaging supply chain capacity enhancement and cost optimizations