Alphawave Semi has a broad selection of leading-edge IP controller blocks and interfaces to which you can add your own custom accelerator, interface, or security IP. For CPU subsystems, we have collaborated with Arm as part of the Arm Total Design ecosystem based on Arm Neoverse Compute Subsystems (CSS) for faster development time with lower risk.
The composable SoC consists of many key subsystems: CPU subsystem, accelerators, memory Interfaces, host interfaces, network interfaces, platform controller, peripherals, and (in the case of chiplets) die-to-die (D2D) interfaces. Each of these can be specifically chosen – or integrated with customer’s IP – and tuned to optimize power and performance for specific workloads. As important as the subsystems themselves is the on-chip interconnect that connects them all together. In the end, balanced performance without bottlenecks between the subsystems and outside world is key to the SoC solution.
Alphawave Semi is taking a leadership role in defining and driving next generation interfaces and standards to advance the computing industry, particularly in the areas of AI/ML. This means you’ll be on the leading edge when these technologies are mature enough to integrate into the composable SoC.
Examples include:
