Interconnect, D2D Communication and I/O Chiplets

Chiplets offer a significant reduction in the total die cost by decomposing a large monolithic integrated circuit into smaller, manageable pieces. This modular approach leverages the fabrication of multiple smaller dies, which are typically less expensive to produce than a single large die due to better yields in the manufacturing process.

The cost-effectiveness of chiplets is most pronounced in designs involving large dies with minimal redundancy. In such cases, the production of a single large die can be economically challenging due to lower yields and higher defect rates, which increase the overall cost. By utilizing chiplets, it’s possible to selectively integrate different application-specific functions into a heterogeneous SoC, each running on a process optimized for both performance and cost. This not only optimizes the performance of each individual component but also enhances the overall system efficiency by tailoring each chiplet to its specific application requirements.

Critically, for AI and hyperscale data centers chiplet architectures not only reduce cost, but also enable SoCs to be developed that exceed the reticle limit and implement increased levels of interconnect. To enable this, foundries such as TSMC and Samsung have developed advanced packaging and assembly techniques, for example CoWoS (Chip on Wafer on Silicon), and die-to-die communication protocols, such as the leading open standard, UCIe, have been created to ensure that the chiplets act as a cohesive system.

As semiconductor processes advance to next-generation nodes, the economic advantages of chiplets are expected to become even more significant. Consequently, adopting a chiplet-based design – with its reduced NRE costs, improved yields and reduced need for the most advanced processes – can lead to significant cost savings compared to manufacturing a larger monolithic die.

Chiplets

Alphawave Semi’s leading IP and custom silicon expertise are integrated into a foundation for prebuilt connectivity chiplets. This cost effective and flexible approach delivers connectivity at a higher bandwidth and lower power than traditional infrastructure solutions. Advanced package technologies have made it possible to intelligently combine various chip functions by stacking die onto a single substrate. Using the N-1 (or even N-2) process for the I/O chiplet can increase savings and decrease time to market by breaking up the SoC into smaller, more efficient building blocks.

AlphaCHIP-I/O

Reconfigurable 112G SerDes I/O with integrated protocol controllers, security IP and UCIe PHY and Controller IP that enables up to 1.6T of throughput at MR, XLR, and PCIe/CXL reaches.

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The 1.6T high-speed I/O chiplet delivers exceptional data throughput, enabling up to 1.6 Tbps per second of bandwidth. Built with multi-protocol 112G SerDes I/O and encompassing integrated protocol controllers and security IP, it caters to the most demanding data transfer requirements. This chiplet ensures that systems can handle massive data volumes with minimal latency, making it ideal for applications in artificial intelligence, machine learning, and big data analytics. Its high-speed capabilities support the rapid scaling of data center operations, contributing to improved performance, efficiency, and the ability to meet future technological advancements without the need for extensive hardware overhauls.

The combo PCIe/CXL/Ethernet chiplet offers remarkable versatility by combining PCI Express (PCIe), Compute Express Link (CXL), and Ethernet protocols into a single, integrated solution. This multi-protocol support allows for seamless communication between processors, accelerators, and networking components. By unifying these interfaces, the chiplet simplifies system architecture, and optimizes data pathways for higher throughput. This is particularly beneficial in high-performance computing and data center environments where workload demands are dynamic, and efficient resource sharing is essential for maximizing computational efficiency.

Leveraging advanced 112G SerDes technology and integrated protocol controllers, it supports data transmission rates up to 1.6Tbps, maintaining high signal integrity over long reaches.

The chiplet provides an efficient solution for transmitting high-speed data over medium distances using optical fibers. By integrating a reconfigurable 112G SerDes I/O with an optimized optical driver optimizations and capability, it enables seamless and reliable communication between devices within data centers or campus networks. This chiplet enhances performance by reducing latency and increasing bandwidth, making it ideal for applications that require swift data exchange without the complexity of long-haul communication systems. Its design simplifies the integration of optical interfaces, leading to cost savings and improved energy efficiency in reaches where copper links fall short in networking scenarios.