1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
The Alphawave PipeCORE PHY IP is a high-performance, low-power, PCIe 1.0 to PCIe 6.0 PHY, that is capable of also operating at 64 Gbps PAM4 PCI Express 6.0 rates (2.5/5/8/16/32/64 GT/s). It includes a hardened PMA layer and a soft PCS layer deliverable. PipeCORE is based on the industry leading AlphaCORE DSP architecture.
PipeCORE is power and performance optimized for the strenuous challenges of PCIe and is targeted to deliver unparalleled bandwidth for the next generation of computing interfaces.
Targeted for 36+ dB of channel loss for 2.5/5/8/16/32/64 GT/s PCIe and CXL rates, PipeCORE delivers a power-optimized, physical layer IP that yields more than 400 Gbps of data throughput per millimeter of silicon perimeter.
Low power, DSP based architecture provides robust operation over long copper backplanes.
Low power DSP architectures enable next generation PCIe Gen6 and CXL interfaces. Supports L1 substate power management. Option power gating implemented.
Integrated microcontroller per lane enables fast PCIe training in both foreground and background adaptation to enable both NRZ and PAM4 rates.
The PipeCORE PCIe PCS layer supports 8b/10b encoding for 2.5/5 GT/s, 128b/130b encoding for 8/16/32 GT/s, and 1b/1b encoding for 64GT/s and has been validated with leading PCIe and CXL Controllers. Supports low latency architecture optimal for CXL applications.
Designed for closed eye, backplane systems up to 45dB of insertion loss at Nyquist with NEXT for NRZ and 38dB for PAM4 PCIe Gen6. Digital CDR meets strict PCIe Jitter Tolerance IO Density.
Built for high performance, PipeCORE is capable of delivering equalization for up to 45 dB channels, while minimizing power consumption for NRZ and PAM4 rates.
Supports 1, 4, 8, and 16 lane configurations, different IP options available for north/south versus east-west orientations. PipeCORE also supports multiple rows of stacking for high density switching applications, and can also support multiple different metal options for SOC flexibility.
Standard CMOS digital devices