Chip-to-Chip Communication for Enterprise and Cloud

I recently had the opportunity to attend a SemiWiki webinar entitled “Chip-to-Chip Communication for Enterprise and Cloud”.  The webinar was presented by SiFive and explored chip-to-chip communication strategies for a variety of applications.  In the first part of the webinar, Ketan Mehta, director of SoC IP product marketing at SiFive explored the uses of the Interlaken protocol. This specification has been around since 2007 and SiFive is on their 8th generation of Interlaken IP. It is the protocol of choice for many demanding data communication applications.

Ketan began with an overview of the markets that can be served by Interlaken IP, which include networking, AI/ML, data center, high-performance computing/cloud. A wide range of markets that all share the need to move more and more data. Looking a bit closer at the problem, we see communication needs driven by massively parallel on-chip systems and chip-to-chip interfaces, the latter requirement is typically driven by the need to decompose a reticle-size chip into a series of smaller die for yield considerations. All these applications demand high performance, low latency data communication.

Ketan then introduced SiFive’s latest low-latency Interlaken IP. He went into quite a bit of detail about the capabilities of this new IP and discussed several real-world examples of where SiFive’s Interlaken IP is used in advanced applications. He concluded with an overview of SiFive’s Interlaken IP portfolio and a discussion of their roadmap.

Next, Sundeep Gupta, senior director of SoC IP at SiFive went into more details about the features and capabilities of SiFive’s Interlaken IP portfolio. As shown in the figure, below, SiFive Interlaken IP supports a broad range of Interlaken Alliance specifications. The IP is also available in two broad types, supporting high-bandwidth and low-latency.

Sundeep discussed in significant detail the key features of this IP portfolio, including performance, SerDes support, forward-error correction (FEC) support, user interface options and many more features. He then presented several block diagrams for various configurations, explaining the structure, data processing and data flow that can be implemented. What comes across during this part or the webinar is the flexibility of this IP portfolio.

Sundeep also went into details about how to create an optimal physical implementation of this IP during place and route. The ability to implement data redundancy was also covered, as well as information of how to use the IP in multi-core configurations, including lane distribution and lane remapping details.

Sundeep then discussed SiFive’s new low-latency IP for Interlaken support. This IP can deliver a 50% reduction in latency as compared with SiFive’s high-bandwidth IP. The features of this IP were covered, as well as an overview of how low-latency performance is achieved. He concluded his presentation with an overview of the deliverables provided by SiFive, summarized in the figure below.

The webinar concluded with a series of very detailed questions that further helped to illustrate the capabilities and roadmap of SiFive. If you’re involved in chip design requiring high-performance data communications, you will get a lot of benefit from this webinar. The good news is that a replay of the event is available here. The run time of the event is under 30 minutes, so you will learn a lot with a small investment in time.