In our previous blog (Part 1) we discussed various interface choices for die-to-die connections. We reviewed how parallel wires are beneficial for chiplet architecture in terms of latency, throughput, and power. Following the selection of a parallel wire interface, two main technologies for parallel interfaces have emerged the past few months, based on packaging choices and throughput requirements.
The first one, OHBI (Open HBI) is an initiative based on silicon interposer. It requires fine ubump pitches of 45-55um with dense signal pitches. This allows for Terabits of throughput between the two dies. OpenFive already announced both PHY and Controller solutions for this technology last year and this has picked up significant customer traction.
The second technology, BoW (Bunch of Wires) is an initiative based on an organic substrate. It supports C4 bumps (130-150um) on organic substrate. There are many new players supporting physical interface using BoW. More details about BoW interface can be found here. We will introduce OpenFive’s link layer controller in this blog and discuss the framing and protocol layer in some more detail.
D2D Controller for BoW
BoW PHY Interface
- BoW uses 20 signal wires, D[15:0], FEC, AUX and a differential clock (DDR), with a maximum per lane
- It is assumed that the PHY implements a 16:1 serialization ratio, resulting in a parallel clock (PLCK) frequency of 1 GHz.
- The FEC and AUX signals are optional.
D2D Framing Layer for BoW
Based on the above PHY layer proposed by the BoW group, below is one way to implement link layer framing function. It considers both FEC and AUX(DBI) as 16-bit signals each from the PHY Slice
The Framing Layer also creates a seamless interface to industry standard SerDes and upcoming parallel interfaces such as BoW, OpenHBI, and AIB. The framing layer also includes optional Forward Error Correction (FEC) blocks.
For more information about OpenFive’s Protocol and Interface Agnostic D2D Controller, click on the following