AresCORE UCIe Die-to-Die PHY IP Factsheet

AresCORE is a market leading extremely low-power, low-latency Universal Chiplet Interconnect Express (UCIe™) Die-to-Die PHY IP designed by Alphawave Semi for very high bandwidth connections between two dies that are on the same package. Its main target applications include, but are not limited to:

  • High-Performance Computing (HPC)
  • Data Centers
  • Artificial Intelligence (AI)
  • Networking

AresCORE UCIe D2D PHY IP is the physical layer to enable Alphawave Semi’s Complete UCIe Solution for an open and robust chiplet ecosystem.

The AresCORE PHY IP is optimized for high-bandwidth density – Up to 36 Gbps data-rate-per-lane, low-power, low-latency multi-module PHY and leverages silicon-proven analog IPs.

The AresCORE PHY IP can be configured to support advanced packaging such as Silicon Interposer, RDL Interposer, Integrated Fan-Out and Silicon Bridge for maximum density, and organic substrates for the most cost-effective solution covering all market segments.

The AresCORE PHY IP is available in leading-edge foundries across multiple technology nodes.

Download AresCORE UCIe D2D PHY IP Factsheet

Download AresCORE UCIe D2D PHY IP Factsheet