Building the Future: Next-Generation Terabit AI Networks with the Industry’s First Multi-Protocol I/O Connectivity Chiplet

Building the Future: Next-Generation Terabit AI Networks with the Industry’s First Multi-Protocol I/O Connectivity Chiplet

Discover how UCIe-enabled chiplet IP subsystems with cutting-edge Multi-Standard SerDes I/O connectivity are transforming the future of AI data networks. As AI computing demands continue to grow, chiplets offer unmatched scalability, efficiency, and innovation to meet these challenges.

What You’ll Learn:

• Overcoming Challenges: Insights into enabling an interoperable 112G Multi-Lane and Multi-Standard I/O chiplet.
• Real-World Implementations: Details and results from the Alphawave Semi Chiplet portfolio.
• Innovative Interconnects: How UCIe Die-to-Die high-density interconnects extend 112G Ethernet and PCIe6 subsystems to seamlessly integrate with the Arm Neoverse Ecosystem.
• Arm CSA Integration: Alphawave Semi’s adoption of the Arm Compute Subsystem (CSS) to develop versatile chiplets that are compliant with the CSA (Chiplet System Architecture)
• Scalability Solutions: Flexible packaging solutions for Arm CSS and Alphawave chiplets to address the diverse needs of AI applications.
• Future Perspectives: Challenges and solutions for scaling up and scaling out connectivity to meet the networking bandwidth demands of next-gen AI systems.

Join us for this insightful session to explore Alphawave Semiand Arm’s solutions and roadmap for revolutionizing AI infrastructure.