High Speed Communications Part 3 – Equalization & MLSD Video

Alphawave’s CTO, Tony Chan Carusone, continues his technical talks on high-speed communications discussing transmitter and receiver wireline circuits required to enable two chips to “talk” with each other – the foundation of communications. Clock recovery and Equalization circuitry are necessary to handle the imperfections and realities that come with real-world implementation and overcome channel losses covered in Part 2. These are commonly known as a Transmit Finite Impulse Response (TX FIR) and Continuous0Time Linear Equalizer (CTLE) is the active equalization found in the Receiver. Instead of communicating faster, PAM4 is discussed, which fits more information into the same unit interval (UI) as a signal transmitting just 0’s and 1’s. Other common DSP received waveform equalization tricks are also discussed, including Discrete Feedback Equalization (DFE) and Maximum Likelihood Sequence Detection (MLSD).