High Speed Communications Part 9 – Anatomy of a Modern SerDes Video

Alphawave’s CTO, Tony Chan Carusone, continues his technical talks on high-speed communications discussing 224 Gbps and beyond. There will be a delicate balance of engineering definition, where conservative overdesign may exceed overall power budgets and under design would obviously result in failures. DSP wireline transceivers are robust and flexible, leveraging the most advanced CMOS technologies. Examples of power scaling DSP receiver are touched upon, maximizing performance at efficient cost. A deep dive of the stages of a modern SerDes are investigated, from the broadband termination to the receiver EQ and the DSP found in the transmitter, and Forward Error Correction (FEC).