SerDes

A SerDes is a pair of functional blocks used in high-speed communications to convert data between serial and parallel forms in both directions.

It is principally used to facilitate the transmission of data over a high-speed serial link by reducing the number of I/O pins required and in doing so, minimize the complexity, cost and the potential signal integrity issues associated with parallel data buses.

Serial links can operate at higher frequencies with improved signal integrity over longer distances compared to parallel buses, which suffer from issues like skew, crosstalk, and electromagnetic interference (EMI) at high speeds. Serial data transmission also simplifies routing on PCBs and facilitates higher data throughput with lower power consumption.

As a result, SerDes is essential when transmitting data between chips and systems, for example via PCIe and Ethernet in a data center setting, as well as between chiplets on an SoC.

Fig 1: The use of SerDes (bottom) minimizes the I/O count, complexity, cost and the potential signal integrity issues associated with parallel data buses

A Brief History of SerDes Technology

The journey of SerDes began in the 1980s with its use in telecommunications, where it facilitated data transmission over fiber optic and coaxial links. By the late 1990s, SerDes technology had evolved to support chip-to-chip communication, replacing traditional parallel links. Over the decades, advancements like PAM4 signalling and ADC-DSP architectures have propelled SerDes to achieve data rates exceeding 100 Gbps, making it indispensable in today’s high-speed communication networks.

Applications of SerDes IP

SerDes IP is integral to a wide range of industries:

Data centers: Facilitates high-speed interconnects for cloud computing and AI workloads.
Telecommunications: Supports 5G infrastructure and high-speed internet services.
Consumer Electronics: Enables seamless connectivity in devices like smartphones and gaming consoles.

Examples of forums developing SerDes applications include:

The Common Electrical I/O (CEI) Implementation Agreement (IA) maintained by the OIF (Optical Internetworking Forum) with six generations published (3.125, 6, 10, 28, 56 and 112 Gbps) already and 224 Gbps development is underway. 448 Gbps solution spaces are also currently being explored by the OIF.
IEEE 802.3 (ba – 25 Gbps, cd – 50 Gbps, ck – 100Gbps, dj – 200 Gbps)
PCIe / PCI SIG (5.0 – 32G, 6.0 - 64G, 7.0 - 128G)

Components of the SerDes

A SerDes system consists of two main components, the transmitter (Tx / serializer) and receiver (Rx / deserializer).

On the transmitter side, the SerDes undertakes a parallel-to-serial conversion, taking parallel data, where multiple bits would be transmitted simultaneously over multiple channels, and converts it into a serial data stream, where bits are sent sequentially over a single channel or differential pair.

The serializer multiplies the clock frequency to match the higher data rate of the serial stream and may use modulation schemes (NRZ, PAM4) to increase data rate while maintaining signal integrity.

On the receiver side, the SerDes reverses this process, taking the high-speed serial data stream and converting it back into parallel data for processing.

Embedded clock information is recovered from the serial data stream to accurately sample the incoming data and maintain synchronization, and any encoding applied during serialization is decoded by the deserializer to recreate the original form.

Fig 2: The transmit and receive functions of SerDes

112G SerDes

112 Gbps SerDes (Serializer/Deserializer) technology is a superset of common electrical I/O from the Optical Internetworking Forum (OIF), with the data rate of 106.25 Gbps being a cornerstone of high-speed data communication for Ethernet applications. It enables efficient data transfer by converting parallel data streams into serial data and vice versa, achieving speeds of up to 112 Gbps per lane. This technology is critical for applications like data centers, high-performance computing, and telecommunications.

Key features of 112 Gbps SerDes include:

PAM4 Modulation: It uses Pulse Amplitude Modulation with four levels, doubling the data rate compared to NRZ (Non-Return-to-Zero) signaling while maintaining the same bandwidth.
Low Power Consumption: Advanced designs focus on minimizing power usage, which is crucial for large-scale deployments.
Scalability: It supports various reach requirements, such as chip-to-chip, chip-to-module, and backplane connections, making it versatile for different system architectures.
Error Correction: Integrated Forward Error Correction (FEC) ensures data integrity over long distances.

The OIF and IEEE 802.3 have been instrumental in standardizing up to 112 Gbps SerDes interfaces, ensuring interoperability across vendors and fostering innovation in the industry. This technology is paving the way for next-generation Ethernet speeds, including 800 Gbps (8 lanes x 100 Gbps) and beyond.

224G SerDes

224 Gbps SerDes technology represents the next leap in high-speed data communication, catering to the demands of advanced Ethernet and Optical Internetworking Forum (OIF) applications, along with emerging standards like Ultra Accelerator Link (UALink). 224G SerDes standards body work started in 2022 and doubles the achievable data rate to 224 Gbps. It builds on the foundation of 112 Gbps SerDes, doubling the data rate per lane to meet the growing needs of hyperscale data centers, high-performance computing, and telecommunications.

Key features of 224 Gbps SerDes include:

PAM4 Signaling: Like its predecessor, it employs Pulse Amplitude Modulation with four levels, but at a higher baud rate, pushing the limits of signal integrity and channel design.
Advanced Signal Integrity Solutions: To address challenges like increased transmission loss and crosstalk, innovative design techniques for packages, PCBs, and connectors are essential.
Power Efficiency: Despite the higher data rates, designs focus on maintaining energy efficiency to support sustainable scaling.
Standardization Efforts: Organizations like IEEE and OIF are actively working on standards to ensure interoperability and drive adoption.

As the world faces increasing I/O bandwidth bottlenecks in applications like AI, building an ecosystem for 224G presents considerable challenges. Compared to earlier generations of CEI, losses increase exponentially at this speed; power consumption of pluggables is also increasing dramatically to compensate for these losses and addressing these complexities. A link training mechanism to synchronize with industry developments aiming to implement link optimizations from host to module may be necessary. Additionally, a collaborative project has been initiated to co-design 224G electrical specifications, with the goal of optimizing every possible margin for future interoperable links, especially as 224G’s VSR loss budgets reach the same complexity level as 112G LR channels in terms of insertion loss.

This technology is pivotal for enabling next-generation Ethernet speeds, such as 1.6 Tbps (8 lanes x 212.5 Gbps) and beyond, and is expected to play a critical role in the evolution of high-density networking systems.

448G SerDes

448 Gbps SerDes technology represents a significant milestone in high-speed data communication, targeting next-generation Ethernet and Optical Internetworking Forum (OIF) applications. It builds upon the advancements of 224 Gbps SerDes, pushing the boundaries of data rates to meet the demands of AI, machine learning, and hyperscale data centers.

Key features of 448 Gbps SerDes include:

Advanced Modulation Techniques: Potentially to employ higher-order modulation schemes, such as PAM6, PAM8 or QAM, to achieve the required data rates while addressing signal integrity challenges.
Innovative Signal Integrity Solutions: Enhanced packaging, PCB design, and interconnect technologies will be critical to mitigate losses and crosstalk at these extreme speeds.
Energy Efficiency: As data rates increase, maintaining power efficiency will be a top priority to ensure scalability and sustainability.
Standardization Efforts: Organizations like OIF are actively exploring frameworks and implementation agreements to define the electrical and optical interfaces for 448 Gbps SerDes.

This technology is expected to play a pivotal role in enabling Ethernet speeds of 3.2 Tbps and beyond, driving innovation in high-density networking systems.

Applications of SerDes

SerDes for die-to-die communication

The core building block of PHYs used in chip-to-chip connectivity, SerDes provides high-bandwidth data transfer between processors, memory, and peripherals.

By serializing data for transmission across fewer wires or traces, SerDes reduces pin count and enhances signal integrity, enabling scalable inter-chip communication. This is crucial for disaggregated networking systems, such as those used in hyperscale data centers, networking, and AI processors, where low-latency and high-throughput connections are required. SerDes in advanced protocols like PCIe and Ethernet ensure interoperability between different chips in complex systems.

Fig 3: Chiplets Powered by Alphawave Semi UCIe D2D and 224G SerDes enable the next generation of switch use cases

SerDes for backplane communication

SerDes is essential for communication between chips within integrated circuits, providing high-bandwidth data transfer between processors, memory, and peripherals. By serializing data for transmission across fewer wires or traces, SerDes reduces pin count and enhances signal integrity, enabling scalable inter-chip communication. This is crucial for multi-chip systems, such as those used in hyperscale data centers, networking, and AI processors, where low-latency and high-throughput connections are required. SerDes and the physical layer definitions are also part of the specifications for PCIe and Ethernet, ensuring interoperability between different chips in complex systems.

These provide the physical layer for interconnecting multiple cards in a chassis, and SerDes enables high-speed, reliable data transfer across these interfaces.

SerDes for optical communication systems

A fundamental element of optical communication systems, SerDes readies data streams for transmission over optical mediums, such as the fibers, waveguides, or mirrors used in optical circuit switches (OCS).

A similar SerDes used for electrical channels may also be used to interface with optical components such as laser diodes and photodetectors, enabling the conversion between electrical and optical signals, which is crucial for long-distance due to the low loss characteristics of fiber, telecom networks and increasingly data centers. It also ensures low-latency, high-bandwidth links to support advanced modulation schemes like PAM4 in order to achieve data rates of 100 Gbps and beyond.

SerDes for data center high-speed interfaces

SerDes is integral to high-speed interfaces like PCIe and Ethernet and enables efficient data transfer at speeds of 100 Gbps and beyond.

As data center workloads increase, SerDes helps to manage the growing need for low-latency, high-bandwidth connections between servers, storage devices, and networking hardware by keeping pin count down. It is optimized for power efficiency and signal integrity, ensuring reliable communication in dense environments with high interconnect complexity. SerDes technology also facilitates scalability in hyperscale data centers by supporting emerging standards such as PCIe 6.0, 7.0 or 100G, 200G and 400G per lane Ethernet.

Technical considerations

SerDes devices are engineered to operate at extremely high data rates, typically in the double- or triple-digit gigabits per second (Gbps) range. This rise increases key challenges, for example signal integrity, power consumption, and EMI.

For example, the latest generations of PCIe and Ethernet require advanced design techniques to minimize errors and maximize efficiency. Engineers must balance bandwidth demands with practical constraints such as heat dissipation, power consumption, and physical limitations of the transmission medium.

Signal integrity challenges

Jitter: In high-speed SerDes systems, even minor timing deviations can cause significant problems and therefore precision clocking, and signal conditioning is vital.
Attenuation: Mitigating attenuation will require the use of equalization and error correction techniques.
Crosstalk: As data rates increase and circuit density becomes higher, shielding, spacing, and careful layouts become crucial in reducing crosstalk.
Reflections: Impedance mismatches in the transmission path will result in some of the signal being reflected back towards the source. This causes distortion and jitter.

Equalization techniques

SerDes (Serializer/Deserializer) systems use equalization to combat the challenges posed by high-speed data transmission over lossy, low-pass filter communication channels. As data rates increase, signal degradation becomes a major issue due to factors like inter-symbol interference (ISI), attenuation and noise. Equalization helps mitigate these effects and ensures reliable data transfer. Following are techniques for implementing equalization:

Transmitter Emphasis (Pre-Emphasis): This technique modifies the transmitted signal by boosting the high-frequency components. It helps counteract the low-pass filtering effect of the channel, reducing intersymbol interference (ISI) and improving signal integrity.
Finite Impulse Response (FIR) Equalization: FIR filters are implemented at the transmitter to shape the signal. They can cancel both pre-cursor and post-cursor ISI, making them effective for high-speed data transmission. However, they require careful tuning and adaptation.
Continuous-Time Linear Equalizer (CTLE): CTLE is used at the receiver to amplify high-frequency signals while attenuating low-frequency noise. It is simple to implement and consumes low power, but its equalization capability is limited to first-order compensation.
Decision Feedback Equalizer (DFE): DFE operates at the receiver and uses previously detected bits to cancel post-cursor ISI. It is effective in reducing noise and crosstalk but can introduce error propagation and latency due to its feedback loop.
Feed-Forward Equalizer (FFE): FFE is implemented at the receiver and applies a linear filter to the incoming signal. It is effective in mitigating ISI without requiring feedback, but it can amplify noise and requires precise coefficient tuning.
Maximum Likelihood Sequence Detection (MLSD): MLSD is an advanced receiver technique that detects the most probable sequence of transmitted symbols based on the observed signal and channel characteristics. It optimally minimizes errors by considering the entire sequence rather than individual symbols, making it highly effective in environments with severe ISI. However, it is computationally complex and power-intensive, which can limit its practical application.
Adaptive Equalization: This dynamic technique responds to variations in the transmission medium caused by changes in temperature, length, or other environmental factors.

Clock recovery

Recovering the clock from the incoming data stream is critical for synchronization between the Tx and Rx. Clock data recovery (CDR) methods include using an embedded clock within the serial data versus employing a separate clock channel. This keeps lane and pin counts low for more area on chips for other functions.

In embedded clock systems, special encoding schemes are used to ensure sufficient transitions for clock extraction. The accuracy of clock recovery directly impacts the system’s ability to handle high data rates without errors.

Encoding schemes

To aid in clock recovery and maintain signal integrity, SerDes systems traditionally implemented encoding schemes like 8b/10b or 64b/66b, and now deploy higher order encoding schemes to reduce the overhead (8b/10b has a 20% overhead). The performance gained from this overhead is typically well worth the extra increase in signalling rate to implement. These schemes help reduce DC bias in the transmission line, facilitate reliable clock extraction and add redundancy, which can be used to detect errors. This is particularly vital in long-distance communication and where signal degradation is of concern.

Considerations When Designing with SerDes

Channel characteristics

The physical medium – such as PCB traces, cables and connectors – can significantly affect signal integrity, especially at high data rates. The length, material properties, and geometry of these interconnects introduce losses, attenuation, and dispersion, which can degrade the quality of the signal. Signal integrity simulations and channel modelling tools are therefore vital.

Impedance matching

This ensures the transmission line’s impedance matches that of the transmitter and receiver, minimizing signal reflections and loss, with mismatched impedance leading to standing waves and reflections.

Protocol compliance

SerDes-based systems must comply with the specific protocol requirements for communication, such as PCIe or Ethernet. Each protocol defines specific parameters, including data rates, encoding schemes, and error correction mechanisms. For example, PCIe 6.0 requires SerDes to handle data rates up to 64 Gbps while supporting PAM4 encoding. The higher data rates of PCIe 6.0 (compared with PCIe 5.0 and before) and the use of PAM4 also means forward error correction is especially critical, with data more susceptible to noise and signal integrity issues.

In PCIe 6.0 must adapt SerDes designs to accommodate the increased sensitivity of PAM4 to jitter, crosstalk, and attenuation, necessitating advanced equalization techniques and more thorough compliance testing.

Testing and validation

After designing a SerDes-based system, extensive testing and validation are necessary to ensure that it operates reliably at the intended data rates. This helps the industry nurture an interoperable ecosystem.

Key techniques include generating eye diagrams, which visually represent the signal’s quality and signal-to-noise ratio, as well as measuring the bit error rate (BER) at the device’s receiver to determine how much stress in the form of jitter, noise, or reduced signal amplitude, it can handle, and how often errors occur.

These can be undertaken with oscilloscopes, noise generators and BER testers, and performance validated under different operating conditions (process, voltage, temperature of the silicon).

Fig 4: Eye diagrams, visually represent the signal’s quality and signal-to-noise ratio

Recent Alphawave Semi SerDes Advances

224G AthenaCORE200 announcement

Alphawave Semi brings High-Speed Connectivity and Compute Solutions at OFC 2025 (link)

Alphawave Semi Tapes Out Industry-First, Multi-Protocol I/O Connectivity Chiplet for High-Performance Compute and AI Infrastructure (link)

Alphawave Semi to Showcase Latest Advances in AI Connectivity IP at ECOC 2024 (link)

Alphawave Semi and InnoLight Extend PCIe over Optics Collaboration with Demonstration of 128 Gbps Gen 7.0 over Low-Latency Linear Pluggable Optics at ECOC 2024 (link)

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