High Speed Communications Part 8 – On Die CMOS Clock Distribution Video

Alphawave’s CTO, Tony Chan Carusone, continues his technical talks on high-speed communications discussing high performance clock distribution, and the challenges that are associated with a typical modern SerDes macro. The increasing use of CMOS clocking has many advantages but is not without disadvantage. There are many types and sources of noise that gets coupled and accumulated into the clock supply, both deterministic and random, which can eventually make its way, potentially amplified, onto the high-speed signal. Tradeoffs in buffer selection over a particular wirelength need to be carefully designed to ensure transmission life effects or RC time-constants aren’t limiting clock performance.