Advances in AI and Connectivity IP from the 2024 Design Automation Conference
The end of June saw a team from Alphawave Semi head to San Francisco’s Moscone Center for the bustling five-day Design Automation Conference (DAC) tradeshow.
DAC is recognised among the world’s leading events for chip and system developers and came hot on the heels of several significant announcements and advances relating to communication standards for AI by Alphawave Semi. June alone saw the unveiling of:
- The tapeout of the industry’s first multi-protocol I/O connectivity chiplet for AI infrastructure, which is developed for TSMC’s 7 nm process and gives a total bandwidth of 1.6 Tbps.
- An Arm® Neoverse™-based advanced compute chiplet for AI, data center and 5G/6G networking infrastructure applications.
- A chiplet-enabled platform that unlocks 1.2 TBps connectivity for AI and HPC infrastructure.
Alphawave also demonstrated IP subsystems for rapid implementation of the 128 Gbps PCIe 7.0 specification, and announced an extended partnership with the Samsung Foundry, which enables the manufacturing of our PCIe 7.0, 112G and 224G Ethernet, and UCIe IP on its most advanced processes, including 2 nm.
We were excited to discuss and demonstrate these and other advanced communication IP technologies, such as our 3nm, 24 Gbps UCIe demonstration and, of course, meeting the designers and system architects that attend DAC to discuss their ideas over a coffee.
DAC was also a key event for our Vice President of IP Product Marketing and Management, Letizia Giuliano, both presenting a paper, and taking part in a panel debate.
Letizia’s paper on UCIe compliance validation examined the complete journey required to achieve this, taking a holistic view from the silicon to the system simulation phase.
Letizia also joined leading voices from the industry – including the Open Computing Project’s Bapi Vinnakota and Cliff Grossner, and the National Energy Research Scientific Computing Center’s John Shalf – to discuss the open chiplet economy and its relevance to AI systems, in particular examining high-performance D2D PHY IP, as well as soft IP for AI.
Alphawave Semi’s Letizia Giuliano presenting during a panel discussion on the open chiplet economy in AI (L) and delivering a paper on UCIe compliance validation (R).
Alphawave Semi’s presence at DAC 2024 was not just about showcasing its technological prowess, but also about working closely with existing and potential customers from across the industry and help them implement the highest-possible performance connectivity.
If you were not at DAC, or if you were unable to attend the Alphawave Semi booth, please get in contact.