Rigorous Correlation Methodology for PCIe Gen5 & Gen6 DSP Based IBIS-AMI Models


IBIS-AMI models have been around for a decade and evolved to provide off-chip and system designers an efficient way to assess link performance of high-speed electrical interfaces with transceivers implementing various combination of equalization techniques [1]. As with any model, for IBIS-AMI to be useful they need to be benchmarked and carefully correlated to real-world silicon performance of the transmitter and receiver they represent. With the advent of multi-standard IPs, modern transceivers can operate over a wide range of operating points on the electrical interface spectrum. Although the underlying architecture of the IP remains the same for different protocols, corresponding to the same IBIS-AMI models, some care needs to be applied when it comes to the correlation and tuning of the underlying behavioral models against silicon performance, as different operating points (e.g., electrical interface, channel loss range and baud rate) dictate different sets of constraints and measurable quantities that are available in a lab environment. The capability to match simulation and real-world performance across not only one operating point but multiple, makes modeling each instantiation that much harder yet that much more necessary to ensure proper operation in these increasingly challenging links. In this paper, we demonstrate a step-by-step correlation methodology adapted for DSP-based PCIe Gen5 and Gen6 IBIS-AMI models where we can measure and directly correlate raw errors out of the DSP on a test setup that is based on the receiver stress eye methodology of the PCIe standard.