GammaCORE is a highly configurable and customizable Universal Chiplet Interconnect Express (UCle™) Die-to-Die Controller IP implementing the latest UCIe 1.1 specification and supporting UCIe Streaming protocol applications.
With Alphawave’s AresCORE D2D PHY IP, GammaCORE provides the complete UCIe solution for an open and robust chiplet ecosystem.
GammaCORE UCIe D2D Controller IP enables multi-die applications, such as the connection of I/O chiplets to a main die, accelerator die to a processor die, multi-die packet processors, multi-die Ethernet switches, etc.
GammaCORE Controller IP core consists of the Streaming Protocol Layer, to extend the SoC interface across the UCIe link, and the Adapter Layer, to provide a reliable end-to-end link.
On the UCIe link side, GammaCORE provides seamless connection to the AresCORE UCIe D2D PHY IP through the RDI interface. On the system side, GammaCORE connects to one or multiple internal SoC interfaces.
GammaCORE supports
- Any specific SOC Interface: AXI4, AXI-S, TileLink, CXS, CHI, and some proprietary interfaces over UCIe.
– Flit and Raw mode operation.
– Configurable datapath width to address specific Bandwidth and target clock frequency requirements.
– Combination with other Alphawave Semi companion IP cores to enable many different configurations.
The GammeCORE Controller IP has been verified against leading UCIe Verification IPs (VIP). The IP is silicon-proven, together with Alphawave’s AresCORE UCIe D2D PHY, on variety of test chips in leading-edge foundries across multiple technology nodes.
The AresCORE UCIe D2D interconnect enables SoC developers to break the boundaries of the reticle limit by including multiple dies in the same package. This multi-die approach to silicon design allows for better yielding, smaller purposeful dies vs. traditional SoCs. The main target applications AresCORE UCIe D2D interconnect include, but are not limited to: