Alphawave’s UCIe Die-to-Die IP Subsystem offers a unique solution with extremely low power, high throughput, and low latency links enabling faster time to integration for heterogenous chiplet connections in wired communications, Artificial Intelligence (AI), High Performance Computing (HPC), Datacenters and Networking applications.
UCIe D2D IP Subsystem is targeted for heterogeneous chiplet solutions. With recent advances in package technologies, it is possible to route high-speed signals within a package connecting multiple dies either on an interposer or on an organic substrate. Alphawave’s UCIe D2D IP Subsystem offers a complete solution with AresCORE UCIe D2D PHY and GammaCORE UCIe D2D controller IPs to enable faster time to integration.
High data-rate-per-lane, up to 36Gbps
Extremely power efficient with less than 0.5 pJ/bit power consumption
Channel lengths support up to 5mm with latency less than 2ns (Other combinations are available)
Comprehensive testability with Built-In Self-Test (BIST), internal and external loopback, and non-destructive eye diagram
Features for KGD (Known Good Die) testing
Adapter (CRC/Retry) based on 256B Latency Optimized Flit format
Streaming protocol for any specific SOC Interface: AXI4, AXI-S, TileLink, CXS, CHI, and some proprietary interfaces over UCIe
Supports both Flit and Raw mode operation
Optional clock domain crossing between SoC and UCIe controller clocks
Configurable datapath width to address specific bandwidth and target clock frequency requirements
Flexible and scalable: any # of ports (multi-ported configs), any # of channels per port, any channel width
Can be combined with other Alphawave Semi companion IP cores to enable many different configurations
